Project 2: Processes and Time-Sharing the CPU on CS 1670: Operating Systems

Appendix A: ARM64 additions

Mon, 01 Jan 0001 00:00:00 +0000

Appendix A: ARM64 additions for Project 2

This appendix covers what is new relative to Project 1’s ARM64 reference, which you should still keep at hand.

Instructions

Instruction	Meaning
`stp x0, x1, [sp, #16]`	Store pair: store two registers at `sp+16` and `sp+24`. Halves the instruction count when saving a context.
`ldp x0, x1, [x2, #16]`	Load pair: the inverse, loads a pair of registers.
`eret`	Exception return. Sets `pc` from `ELR_ELn` and `PSTATE` from `SPSR_ELn` (for the current exception level n) in one step. Used both to drop an exception level and to resume a saved context.
`msr DAIFSET, #2`	Mask (disable) interrupts. The immediate is a 4-bit selector over the `PSTATE` mask bits: 8 = Debug, 4 = SError, 2 = IRQ, 1 = FIQ. So `#2` touches only the IRQ mask.
`msr DAIFCLR, #2`	Unmask (enable) interrupts; same selector encoding.
`wfi` / `wfe`	Wait for interrupt / event: put the core in a low-power state until something happens. A good way to park a CPU core that has nothing to do.
`svc #0`	Supervisor call: deliberately raise a synchronous exception. This is how system calls will work in Project 4; here it is useful for testing your exception vector table.
`.balign N`	(An assembler directive, not an instruction.) Advance to the next address that is a multiple of `N`, padding as needed. Essential for laying out an exception vector table.

System registers

Remember that all of these are read with mrs and written with msr, never mov, and that most of them exist separately at each exception level.

Appendix B: Hardware Manuals

Mon, 01 Jan 0001 00:00:00 +0000

Appendix B: Hardware manuals for Project 2

Project 1 needed one manual; this project needs three, because the pieces of hardware you are programming belong to different vendors.

1. The Arm Architecture Reference Manual for A-profile (ARMv8-A). This is the authority on everything in Appendix A: exception levels, the exception model, the vector table layout, PSTATE, and the generic timer. It is several thousand pages long and you should not read it linearly. The chapters you may be interested in are the ones on the AArch64 exception model (what the CPU does on an exception; the vector table) and on the generic timer (the CNT* registers). The register descriptions are in the “AArch64 System Register Descriptions” part, alphabetically. While you can use it, we instead recommend Jon Palmisciano’s ARM reference, which contains the same information but makes it searchable and presents it more compactly.

Appendix C: Debugging Concurrency

Mon, 01 Jan 0001 00:00:00 +0000

Appendix C: Debugging concurrency

Everything in Project 1’s testing and debugging appendix still applies. What follows is the additional toolkit for this project, where bugs are no longer purely about what your code does but also about when.

Appendix D: Assertions and Debug Output

Mon, 01 Jan 0001 00:00:00 +0000

Appendix D: Assertions and debug output

Kernel bugs are unusually hard to find, and this project makes your kernel much more complex, which invites new classes of bugs. Because your OS doesn’t have memory protection yet, a bug can quietly corrupt memory and the machine misbehaves thousands of instructions later in code that is entirely innocent. And there is concurrency, so the misbehaviour may not even show up in the same process as the bug.