Appendix B: Hardware manuals for Project 2

Project 1 needed one manual; this project needs three, because the pieces of hardware you are programming belong to different vendors.

1. The Arm Architecture Reference Manual for A-profile (ARMv8-A). This is the authority on everything in Appendix A: exception levels, the exception model, the vector table layout, PSTATE, and the generic timer. It is several thousand pages long and you should not read it linearly. The chapters you may be interested in are the ones on the AArch64 exception model (what the CPU does on an exception; the vector table) and on the generic timer (the CNT* registers). The register descriptions are in the “AArch64 System Register Descriptions” part, alphabetically. While you can use it, we instead recommend Jon Palmisciano’s ARM reference, which contains the same information but makes it searchable and presents it more compactly.

Arm’s Learn the architecture guides are considerably friendlier than the reference manual and are correct; the guide on AArch64 exception handling is a good half-hour investment before Quest 4.

2. The BCM2836/BCM2837 ARM-local peripherals document (often called “QA7”, after its original filename QA7_rev3.4.pdf). You need this, and only this, for Quest 4 Part C.

The BCM2835 peripheral manual you used in Project 1 documents the peripherals hanging off the SoC—GPIO, UART, the system timer. It does not document the hardware that sits between the ARM cores and those peripherals: the per-core interrupt routing, the mailboxes, and the per-core timer control. That is what this second document covers, and it is why you will not find the “Core 0 timers interrupt control” register in the manual you already have.

• Its registers are based at 0x4000'0000.
• The sections you need describe the per-core timer interrupt control registers and the per-core interrupt source registers. Both are short; the register bit tables tell you which bit corresponds to which of the four generic timers (secure physical, non-secure physical, hypervisor, virtual) and whether it is routed as an IRQ or an FIQ. You want the non-secure physical timer, as an IRQ, for core 0.

3. The BCM2835 ARM Peripherals manual, which you already know from Project 1. You will not need it for the required quests, but it can be helpful for extra credit quests.